1. Field of the Invention
The invention relates to computer architecture, hardware and method and in particular, to computer architecture, hardware and method that eliminates the need for an operating system.
2. Background of the Invention
FIG. 1 illustrates a conventional computer system architecture 100 comprising a hardware platform layer 200, a firmware layer 300, an operating system layer 400 and an application programs layer 102. The hardware platform layer 200 is the physical layer of the computer system that performs the actual operations of the computer system. The firmware layer 300 performs, among others, the interface between the hardware platform layer 200 and the operating system layer 400. The operating system layer 400 is a software layer that performs the management of the computer resources such as processor resource management, memory allocation management, device resources management, and data file management. The operating system is also the base upon which application programs are built. The application programs layer 102 comprises computer programs that provide instruction sets that manipulate and/or process data in accordance with a desired result. Examples are word processor, database, spread sheet and web browser programs.
FIG. 2 illustrates a conventional hardware platform layer, also commonly referred to as a xe2x80x9ccomputerxe2x80x9d) 200 of a computer system comprising a central processing unit (CPU) 202, a read only memory (ROM) 204 and a main memory 206 coupled together through a system bus 208. The illustrated configuration is representative of a bus architecture type computer system that is commonly used and includes Personal Computer Interface (PCI), Industry Standard Architecture (ISA), Extended ISA (ESIA) and other bus standards. The computer 200 need not be limited to a bus architecture and may use a different architecture. The computer 200 further comprises various controllers such as a memory controller 212, a direct memory access (DMA) controller 214, an interrupt controller 216, an input/output (I/O) controller 218, an integrated drive electronics/floppy drive controller (IDE/FDC) controller 222 and a video controller 224, among others. Various devices are coupled to the controllers so that the computer 200 can interact with a user or with the outside world. For instance, a video monitor 226 is coupled to the video controller 224 to display various information, a keyboard 228 and a pointing device 232 is coupled to the I/O controller 218 via a serial port to input data and commands to the computer 200, a printer 234 is also coupled to the I/O controller 218 via a parallel port to generate hard copies of data requested by the user. The IDE/FDC controller 222 controls various disk drives such as a diskette drive 236, a hard-disk drive 238, a compact disc (CD) ROM drive 242 and a digital video disc (DVD) ROM drive 244 and a modem 246 provides communication to the outside world such as the Internet. Typically, the hardware has one or more expansion slots 248 to receive various expansion cards that enhance or add features of the hardware platform, thus a modem card 246 may be inserted into the expansion slot 248 to provide a communications feature.
The firmware layer such as a Basic Input Output Operating System (BIOS) 300 may be located in the ROM 204 and is generally specific to the hardware platform of the computer that it supports. The BIOS routines include various setup procedures and Power On Self Test (POST). The various setup procedures include the configuration of the various controllers in which the BIOS acts as an uniform interface between the controllers and the operating system, thus allows the operating system to access the hardware platform 200. The BIOS supports the interchange of data that uses the various controllers, devices such as keyboard, mouse, video monitor, disk drives, printer and so forth. Other setup procedures include preliminary memory setup for the operating system, fault handling, clock and timers for various circuits, for example, the dynamic random access memory (DRAM) refresh circuit that refreshes the DRAMs that comprise the main memory. The POST performs various self-test on the memory and controllers and if a fault is find during the self-test, an error message in a form of an audio beep and/or a error message is displayed.
FIG. 3 is a flow chart of an exemplary power-up sequence using the BIOS that may conform to Compaq Computer Corporation, Phoenix Technologies Ltd. and Intel Corporation, Plug and Play BIOS Specification, Version 1.0a, May 5, 1994, which is incorporated herein by reference. The BIOS may also conform to Intel Corporation and Microsoft Corporation, Plug and Play ISA Specification, Version 1.0a, May 5, 1994, which is incorporated herein by reference. Plug and Play (PnP) specification allows for a computer operated configuration of devices attached to the computer without manual manipulation by a user. The user can add a new device, such as a sound card, and the computer will automatically detect the device and provide a device driver to operate the card (which may include requesting the user to insert a disk or a CD that contains the device driver if the computer does not already have the driver internally). A PnP conforming device usually has the characteristics of being able to uniquely identify itself; indicate the services it provides and the resources it requires; identify the device driver that supports it; and an operating system to control the device. These features are important to the operating system in that they allow the operating system to establish a working configuration for all devices connected to the computer and to load appropriate device drivers into memory.
Device drivers are software modules comprising logic for controlling the low level or specific components of a device, thus allowing the operating system to control the device. For example, a device driver may be used for controlling a magnetic disk drive coupled to the computer. In this example, the device driver will control various hardware specific registers, latches, signals or other components of the magnetic disk drive device. A device driver is usually specifically configured to communicate with a particular device.
Referring now to FIG. 3, according to one power-up sequence, at stage 302, the computer is powered on or a reset signal is received in which the computer forces the components within the computer including accessible devices to a reset logic state. At reset logic state, the computer does not xe2x80x9cknowxe2x80x9d its actual configuration including what devices including those on the expansion cards are attached to the computer. After a predefined period of time has passed in which the power supply has stabilized, at stage 304, the CPU starts at a starter address that points to the ROM in which the BIOS is located. The POST routine of the BIOS is initiated and it tests the dynamic random access memories (DRAMS) that make up the main memory along with certain devices and components of the system to determine their operability. During the testing process, a copy of the BIOS is retrieved from the ROM and is shadowed into the main memory. The BIOS has a set of instruction routines that prepares the computer system to receive the operating system from an initial load device (IPL) which may be a disk drive. At stage 306, the BIOS attempts turn off all the devices to determine which devices (i.e. IPLs) may be used to find and launch the operating system. IPLs are detected at this stage because IPLs cannot be turned off. At stage 308, the BIOS turns on the devices and places non-IPLS in wait state to be initialized by the operating system. At stage 310, the BIOS executes a bootstrap routine that causes the kernel of the operating system (usually contained in the hard-disk drive) to load into the main memory. At this stage, the hardware control by the firmware (i.e., the BIOS) is passed to the software (which is the kernel). The kernel 402 provides the core function of the operating system which is computer resource management such as process execution, memory management, dynamic linked library management, scheduling, file system management, I/O services and user interface presentation, among others.
At stage 312, the kernel initiates an isolation procedure that isolates the devices individually. The key to the isolation protocol is that each device contains a unique 72-bit number known as a serial identifier. Once a device is isolated, it is assigned a Card Serial number (CSN) that is unique to the assigned device and serves as a xe2x80x9chandlexe2x80x9d in which the operating system identifies the device and with which the device identifies itself, for instance when generating an interrupt. At stage 314, the kernel reads the isolated devices individually for resource requirements of the device. The resources required by the devices include DMA, interrupt request (IRQs), I/O and memory addresses. At stage 316, the kernel creates a comprehensive list of the resource requirements of each device. At stage 318, because the kernel knows the available system resources, the kernel allocates the available resources to the devices as needed while ensuring the resource allocation is non-conflicting. At stage 320, as the kernel allocates system resources to the devices an allocation map is created and stored in memory. In addition to the creation of the allocation map, At stage 322, using the identification number provided by the device, the kernel identifies the associated device driver that is usually stored in the hard-disk drive. Should the device driver be unavailable, the kernel will prompt the user to provide the device driver. All device drivers associated with the detected devices are loaded into the main memory which is used by the kernel to control the devices. Further details of the power-up sequences may be found in Plug and Play ISA Specification. The isolation, interrogation of the various devices and loading of the device drivers into the main memory is time consuming and also reduces the available main memory.
FIG. 4 illustrates a schematic diagram of an operating system 400 comprising a kernel 402, a device drivers layer 404, an application program interface (API) 406 and a library layer 408. The kernel 402 provides the core function of the operating system as mentioned with respect to FIG. 3. Application programs directly or indirectly rely on these and other capabilities of the kernel and other portions of the operating system. The device drivers layer 404 contains the device drivers necessary to control and communicate with devices. The operating system also provides the interface between the hardware and the application programs layer. To facilitate development of application programs, the operating system also includes application program interfaces (APIs) 406 to interact with application programs. An API is a set of routines that application programs use to access lower level services performed by the operating system. The operating system performs a number of services for the application programs including module management, inter-process communication (IPC) and scheduling. Another service provided is the dynamic linked libraries (DLL) contained in the library layer 408. The operating system performs module management by supporting the linking, loading and execution of DLLs available in the library layer.
The operating system also organizes the instructions from application programs into chunks called threads. A thread can be thought of as a packet of instructions that can be xe2x80x9cchewedxe2x80x9d for execution by the CPU. The operating system breaks the operation of multiple application programs into threads for sequential execution thus allowing the CPU to simultaneously support several application programs known as multi-tasking. Multi-tasking in one example increases the speed of a computers operation by allowing various devices to operate without idling the CPU. Usually, the CPU executes instructions much more quickly than data can be read and written into a storage device. Thus, the CPU would be idle if it had to wait for data to be written or read from a storage device. The use of threads allow the operating system to reassign the CPU whenever a task must be performed for a slow component of the system. For example, the processing of instructions from a first application program may be suspended whenever data must be read from a disk drive. The CPU may then execute a thread from another application program while the data is being read, and resume processing of the instructions from the first application program, once the data has been read.
The computer using a bus architecture usually has one bus in which the CPU and the various devices communicate through. Thus, the operating system controls a flow of instructions to the CPU from application programs, and temporal suspension of CPU processing of application program instructions to allow for the I/O communication by various devices such as the data transfer from the disk drive to the main memory via the DMA controller.
The computer system using an operating system described above has an undesirable lengthy power-up sequence that inconveniences the user and consumes valuable memory space. A known method uses a faster CPU to speedup the power-up sequence. However, a faster CPU is expensive and increases the cost of the computer. The computer system relying on the operating system is subject to xe2x80x9ccrashesxe2x80x9d perhaps due to a tainted application program it had executed, or due to errors resulting from handling numerous interrupts and call procedures during multi-tasking. In addition, the operating system is subject to virus attacks that may render the computer system inoperational as well as destroying valuable data files. What is needed is a computer system and method that solves these and other shortcomings.
Embodiments of the present invention provides computer architecture, hardware and method that eliminates a need for an operating system.
In one general aspect, a computer system comprises a central processing unit (CPU), a main memory, a further unit that includes a first microcontroller and a first memory containing a first set of instructions configured to cause the microcontroller to manage CPU operations, and a plurality of trace links connecting the further unit to the CPU and the main memory to facilitate communication between the further unit, the CPU and the main memory. Other features include at least one device, a trace link connecting the device to the further unit, and the further unit further includes a second microcontroller and a second memory containing a second set of instructions configured to cause the second microcontroller to manage the device; the further unit further includes a third microcontroller and a third memory containing a third set of instructions configured to cause the third microcontroller to manage memory operations; the further unit further includes a fourth controller and a fourth memory containing a fourth set of instructions configured to cause the fourth controller to manage data operations; the plurality of microcontrollers in the further unit are connected together to communicate with each other; the further unit includes a cross-bar switch to connect the plurality of microcontrollers; the device includes a fifth microcontroller and a fifth memory containing a fifth set of instructions configured to cause the fifth microcontroller to control the device operations, the fifth microcontroller in communication with at least the second microcontroller; the fifth set of instructions in the fifth memory further configured to cause the fifth microcontroller to test the device and if the device is operational the fifth set of instructions is configured to cause the fifth microcontroller to signal at least the second microcontroller to indicate availability of the device; the fifth set of instructions in the fifth memory further configured to cause the fifth microcontroller to signal at least the second microcontroller to indicate availability of the device includes sending device identification and required resource data; the second set of instructions in the second memory further configured to cause the second microcontroller to receive the signal indicating availability of the device and allocating available resources to the device.
In another aspect of the invention an apparatus for managing computer operations comprises a first microcontroller and a first memory containing a first set of instructions configured to cause the microcontroller to manage central processing unit (CPU) operations.
Other features include a second microcontroller and a second memory containing a second set of instructions configured to cause the second microcontroller to manage device operations; a third microcontroller and a third memory containing a third set of instructions configured to cause the third microcontroller to manage memory operations; a fourth controller and a fourth memory containing a fourth set of instructions configured to cause the fourth controller to manage data operations; the plurality of microcontrollers are connected together to communicate with each other; a cross-bar switch to connect the plurality of microcontrollers; wherein the memory is a read only memory (ROM); wherein the memory is an erasable programmable ROM (EPROM); wherein the memory is a Flash memory; wherein the microcontrollers are digital signal processors (DSPs); wherein the apparatus is contained in a semiconductor chip; a device including a fifth microcontroller and a fifth memory containing a fifth set of instructions configured to cause the fifth microcontroller to control the device operations, the fifth microcontroller in communication with at least the second microcontroller; the fifth set of instructions in the fifth memory further configured to cause the fifth microcontroller to test the device and if the device is operational the fifth set of instructions is configured to cause the fifth microcontroller to signal at least the second microcontroller to indicate availability of the device; the fifth set of instructions in the fifth memory further configured to cause the fifth microcontroller to signal at least the second microcontroller to indicate availability of the device includes sending device identification and required resource data; the second set of instructions in the second memory further configured to cause the second microcontroller to receive the signal indicating availability of the device and allocating available resources to the device.
In another aspect of the invention a device for use in a computer system that eliminates a need for an operating system comprises device circuitry, a first microcontroller and a memory containing a set of instructions configured to cause the microcontroller to control device circuitry, the instructions further configured to facilitate the microcontroller to communicate with a second microcontroller that manages a central processing unit (CPU) operation.